Today's integrated circuits include a vast number of devices. Smaller and faster devices arising from current device scaling are key to enhance performance, but it is also vital to improve or at least maintain its reliability as well. However, as MOSFET, (Metal Oxide Semiconductor Field-Effect-Transistor, a name with historic connotations meaning in general an insulated gate Field-Effect-Transistor [FET]) and in general FET, devices are being scaled down, the technology becomes more complex and changes in device structures and new fabrication methods are needed in order to maintain the expected performance enhancement from one generation of devices to the next. In this regard the semiconductor that has progressed the farthest is the primary semiconducting material of microelectronics, silicon (Si), or more broadly, Si based materials. One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy.
There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Several avenues are being explored for keeping device performance improvements on track. Among these is the use of either tensilely or compressively strained Si as the basic semiconducting device material having enhanced carrier mobility for electrons and holes in comparison to bulk Si transport. Further improvements can be achieved by alloying Si with Ge. Additionally, a further commonly used scheme is to build devices in a semiconducting layer which is isolated from the semiconducting substrate by a buried insulating layer. Most commonly the semiconducting layer is Si, hence the terminology SOI (Si on insulator) is generally in use, and the buried insulator is SiO2, to yield the name of BOX (buried oxide). However, there are still many outstanding issues in achieving the highest possible performance in deeply submicron MOSFET devices.
As the gate insulator is thinned, as dictated by the requirements of ever smaller devices, there is the problem of the doping impurities penetrating the gate insulator, typically an SiO2 layer. For the sake of optimal device design, the gate typically is made of polysilicon, which is doped the same conductivity type as the device itself. With such doping the resultant workfunction of the gate with respect to the channel region of the device allows for the threshold of the device to be optimally set. Accordingly, N-type devices are in need of N-doped gates, and P-type devices are in need of P-doped gates. During the high temperatures of device manufacturing, the gate-doping species, most problematically boron, (B), but others like phosphorus (P) as well, readily penetrate the thin gate insulator and destroys the device. The gate insulator in modern high performance devices typically needs to be less than about 3 nm thick. Preventing this dopant penetration would be an important step in achieving thinner gate insulators.
In this invention when the strained monocrystalline layer which is hosting the critical parts of the devices, such as the channel regions, is referred to as a SiGe layer it is understood that an essentially pure Si or Ge layer is included in this terminology.
For high device performance the resistance of a turned on device must be as low as possible. With smaller devices the intrinsic resistance of the device itself is decreasing, but other, so called parasitic, resistances have to be taken care of. One such resistance arises from the source terminal of the device. To minimize both the source and drain resistance, these device regions are typically implanted and then silicided during device fabrication. However, the consumption of too much Si during the silicidation process has, and does create drawbacks of its own. In SOI technologies, where the device is purposely built in a thin device layer over an insulator, this problem is especially acute. The silicide formation can easily consume the whole portion of the thin device layer in the source and drain regions. Therefore, there is a need for making the semiconductor device layer thicker especially in the source and drain regions, or find other means to reduce the effect of the source resistance.
With shortening gate lengths the so called short channel effects, most notably the “drain induced barrier lowering” (DIBL) pose severe roadblocks to miniaturization. These effects can be mitigated by introducing basic structural changes in the devices, leading to the use of multiple gates. However, this approach can only yield the desired performance improvements if it is appropriately coupled with other high performance techniques, a problem still looking for solutions.